CV

Education

• B.S. in Electronics and Communications Engineering, Cair University, Faculty of Engineering, 2025

Skills

• HDL
  • Verilog
  • SystemVerilog
• Programing Languages
  • C
  • C++
  • Python
  • MATLAB
• Scripting
  • TCL
• Tools
  • Multisim
  • QuestaSim
  • Vivado
  • Cadence

Projects

• AES-128: Advanced encryption standard design and implementation in Verilog.
• Spartan6-DSP48A1: RTL code for Spartan6-DSP48A1 with Verilog.
• SPI Slave with RAM: RTL code for SPI Slave with RAM with Verilog.
• RTL For Single - Multi Cycle MIPS Processor: Write the RTL code for MIPS processor with Verilog.
• Client Queue System with Verilg: RTL code for Client Queue to to display various information about the status of the queue with Verilog.